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SCLT3-8BT8
Protected digital input termination with serialized state transfer
Features

8-input circuit in common ground low side topology Wide range input DC voltage VI : -30 V to 35 V - On state threshold : < 11 V with RI = 2.2 k - Off state threshold: Iin > 1.5 mA or Vi > 5 V - Protected against -30 V reverse polarity 2.35 mA active current limiter with 10% tolerance - Drastic dissipation reduction: 78 mW max. per input Input digital filter with adjustable delay: 20 s to 3 ms Energy-less LED visual status driver Input logic state transfer through a 2 MHz SPI - Programmable 8 / 16-bit register length - Multi SCLT connection in daisy chain - Chip temperature OTA and under voltage UVA alarms - Multi parity bits and power loss detection with stop bits - Drastic reduction of isolated coupler count and I/O of the field bus ASIC Power supply and input protection, RI = 2.2 k: - IEC 61000-4-4 transient burst : 4 kV minimum - IEC 61000-4-5 voltage surge: 1 kV minimum - IEC 61000-4-2 ESD: 8 kV in contact: 15 kV in air minimum Wide range power supply voltage VC: - + 9 V to + 35 V with 10 mA output current - Protected against -30 V reverse polarity
SCLT3-8BT8 HTSSOP-38

Applications

Digital inputs for programmable logic controller and decentralized I/O modules Digital input with serialized state transfer Enabling digital inputs to meet type 1 and 3 characteristics of IEC 61131-2 EN60947-5-2 2-wire proximity sensor compatibility
Description
The SCLT3-8BT8 provides an 8-line protected digital input termination with serialized state transfer. This device enhances the I/O module density by cutting the dissipation (78 mW per input) and reducing the count of opto-transistors. An adjustable digital filter and an LED driver are embedded in each type 3 input section. Its 2 MHz SPI peripheral output serializes the input state transfer to the I/O module controller.
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Contents
SCLT3-8BT8
Contents
1 Circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 I/O pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 2.3 2.4 2.5 Input power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Visual input LED driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 The input digital filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Operation of the SCLT with the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SPI bus signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 Chip select /CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Serial clock SCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Serial data input MOSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Serial data output MISO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPI shift register operation selector SPM . . . . . . . . . . . . . . . . . . . . . . . 11
2.6
SPI data transfer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.6.1 2.6.2 2.6.3 SPI data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SPI data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SPI transfer speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.7
Control bit signals of the SPI transferred data frame . . . . . . . . . . . . . . . . 13
2.7.1 2.7.2 2.7.3 2.7.4 2.7.5 Power bus voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Over temperature alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Parity checksum bits calculation and transfer . . . . . . . . . . . . . . . . . . . . 14 SPI hardware interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Loss of VCC power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Application considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1 3.2 3.3 3.4 3.5 SCLT serial link configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1.1 Interfacing the SPI section to the I/O controller through optotransistors 25
High speed operation with magnetic isolators . . . . . . . . . . . . . . . . . . . . . 25 Reverse polarity robustness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Surge voltage immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Fast transient burst immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5.1 Considerations on the power section . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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SCLT3-8BT8 3.5.2
Contents Considerations on the logic section . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.6 3.7 3.8
Under voltage alarm setting for IEC and device-net applications . . . . . . . 27 Input operation for the device-net applications . . . . . . . . . . . . . . . . . . . . . 28 Dissipation calculation in the SCLT3-8 circuit . . . . . . . . . . . . . . . . . . . . . . 28
4 5 6 7
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Circuit block diagram
SCLT3-8BT8
1
Circuit block diagram
Figure 1. Circuit block diagram
VDD
IN1
Protected input
VDD MISO
Input state register
Data state register
VR
LD1
VIN < V R
/MISO
VDD
16 s / 3 ms digital filters
8 lines
8 lines
COMS MOSI SCK
COMP
WRITE SHIFT
CAPTURE
Protected input
I = 2 to 8
8 lines
Transfer logic
INI
MOSI SHIFT
/CS SPM VC
7 lines
Control state register
LDI
16-bit
Parity bits gen.
4 lines
REF DVR OSC
Current reference
Power reset
Power supply
VDD
Under voltage alarm
Oscillator
8 / 64
Clock divider
Over temperature alarm
VCS
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Circuit block diagram
1.1
I/O pin descriptions
Table 1.
Name INI LDI VC VCS COMP VDD COMS REF DVR OSC SPM /CS SCK MOSI /MISO MISO SUB NC
I/O pin descriptions
Type Power input Power output Power input Signal input Ground Description Logic input with a current regulation behavior, I = 1 to 8 LED output driver with a current regulation behavior, I = 1 to 8 24 V sensor power supply 24 V sensor power supply sensing input Power ground of power sensor supply Pin # 8 to 11, 13 to 16 20 to 27 5 6 4, 7, 12, 17 38 30 29 1 2 3 35 34 33 32 31 Exposed pad 18, 19, 28, 36, 37
Power output 5 V logic power supply Ground Signal input Logic input Signal input Signal input Logic input Logic input Logic output Logic output Logic input Substrate Signal ground of logic / output section Input current limiter reference setting Divider ratio selector of the digital input filters (8 or 64 steps) Delay setting of the digital input filters SPI shift register length selector (8 or 16 bits) SPI chip Select signal SPI serial clock signal SPI serial data input signal Inverting SPI serial data output signal SPI serial data input signal Exposed pad: connected to die substrate, to connect to COMPP Not connected (or to be connected to COMP)
Figure 2.
Pinout description of the HTSSOP-38 version (top view)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
DVR OSC SPM COMP VC VCS COMP IN1 IN2 IN3 IN4 COMP IN5 IN6 IN7 IN8 COMP NC NC SUB SUB
VDD NC NC /CS SCK MOSI /MISO MISO COMS REF NC LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20
SCLT3 -8BT8
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Circuit block diagram Figure 3. Basic application diagram
SCLT3-8BT8
RS RPD
VCS VC
UVA
SPI
SCLT3 -8
VDD
RC
COMP
Voltage regulator
COMS
RI
Digital filters
8 / 16-bit State transfer SPI
CPHA = 0 CPOL = 0
8-input type 1/3 CLT
IN8 RREF REF DVR LD1 LD8
/CS
O-T
MISO
O-T
/MISO MOSI SPM
OSC O-T = opto-transistor or isolator
Figure 4.
Basic module input characteristics in type 3
30 25 20 15 11V 10 OFF 5 0 0 0.5 1 1.5 IIN (mA) 2 2.5 3
VI (V)
RI = 2.2 k VI = V IN + RI x IIN
RI SCLT
2.1mA
2.6mA
ON
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Field bus controller
IN1
SCK
O-T
SCLT3-8BT8
Functional description
2
2.1
Functional description
Input power section
The SCLT3-8 is an 8-line input termination device designed for 24 V DC automation applications. It provides the front-end circuitry of a digital input module (I/O) in industrial automation. Available in an eight-channel configuration, it offers a high-density termination by minimizing the conducting dissipation and the external component count. Made of an input voltage protection, a serial current limiting circuit and an output interface, each channel circuit terminates the connection between the logic input and its associated high side sensor or switch. The SCLT3-8 is an 8-line current limiting input array compatible with type 1 and 3 (>2 mA) characteristics of the IEC 61131-2 standard. Each input voltage clamping block protects the module input against electromagnetic interferences such as those described in the IEC 61131-2 standard and IEC 61000-4-2 (ESD), 4-4 (transient burst), 4-5 (voltage surge) and 4-6 (conducted radio frequency interferences) standards. The supply input is also designed with such a protection structure. The current limiting circuit connected between the INI and LDI pins is set externally by a resistor RREF and is compensated over the full temperature range. Thanks to its 10% tolerance, the current limitation allows drastic reduction of the input dissipation, 78 mW per channel in type 3, compared with a resistive input. Furthermore, the SCLT3-8 is housed in a very low RTH exposed pad HTSSOP surface mount package that allows the PCB cooling pad to be reduced. The overall module and printed board size become smaller and the hot spot effect is reduced. In accordance with IEC 61131-2 standard when the input current is less than 1.5 mA, the output circuit maintains the associated output data and the visual LED in the OFF state. When the module input voltage VI, including the 2.2 k input resistor, is higher than 11 V corresponding to a SCLT input voltage VIN higher than 5 V, the output circuit puts its associated output data in ON state.
2.2
Visual input LED driver
Since the inputs are indicated with an LED, as described in the IEC 61131-2 standard, an LED driver is implemented on each input power section. This driver has two major benefits for the application. First, it takes its electrical energy directly from the input current. This energy is free being, in any case, dissipated in the SCLT. Second, it eliminates the need for extra pins on the I/O controller to manage the LED drive. The LED will be powered when the input voltage VI is higher than 11 V, and it is turned off when the input current is less than 1.5 mA. The LED diodes will be driven in a low side configuration, all cathodes connected to ground. This topology naturally protects the LEDs and simplifies their wiring (8 wires plus the ground wire). When the LEDs are not used, the pins LDI are grounded to COMP to maintain the path of the input current.
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Functional description Figure 5.
SCLT3-8BT8 Low side front-end input topology including the ESD surge protection and the LED driver
IN
VR
Filter
LD
COMP
2.3
The input digital filter
A digital filter is implemented between the input state comparator and the input state register. It consists of a 2-step sampling circuit that is controlled by an oscillator as shown on Figure 6. The filtering time tFT is set by the external oscillator resistor and is a function of the oscillator period tCKF: 2 x tCKF < tFT < 3 x tCKF tCKF = Divider ratio x tOSC (ROSC) This period can be adjusted between 20 s and 3000 s and is compatible with the IEC 61131-2 standard as shown on Table 2. Table 2. Typical setting of the digital filter timings
Fast 60 kHz 20 s 51 k 10 s COMS 8 20 kHz 50 s 150 k 25 s COMS 8 Medium 5 kHz 230 s 82 k 115 s VDD 64 Slow 300 Hz 3.0 ms 1.3 M 1500 s VDD 64
Input speed Input frequency Min. filter time tFT OSC resistance CKF period tCKF DVR connection Divider ratio
Being placed in the front end of the module, this filter increases the transient immunity of the SCLT and its SPI logic circuitry. It also simplifies the input management software task of the ASIC controller.
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SCLT3-8BT8 Figure 6.
Functional description Two-step digital filter placed after the analog section of the logic input
IN
D CK
Q /Q
D CK
Q /Q
D CK
Q /Q
S Q R
OUT
CKF
CKF
IN
OUT
2.4
Operation of the SCLT with the SPI bus
The SPI bus master controller manages the data transfer with the chip select signal /CS and controls the data shift in the register with the clock SCK signal. This data transfer operation is defined by the phase CPHA and the polarity CPOL of the clock. The SCLT runs with an SPI master protocol mode: CPHA = 0 and CPOL = 0. Figure 7. Serial data format frame with a master running in CPHA = 0 and CPOL = 0 mode
CS SCK
1
2
3
4
13
14
15
16
MOSI
MSBM
14
13
12
3
2
1
LSBM
MSBS
MISO DATA CAPTURE
MSBS 1
14 2
13 3
12 4
3 13
2 14
1 15
LSBS 16
MSBM
The transfer of the SCLT input state in the SPI register starts when the chip select signal /CS falls and ends when this chip select signal rises back. The transfer of data out of the SCLT slave MISO output starts immediately when the chip select signal /CS goes low. The input MOSI is captured and presented to the shift register on each rising edge of the clock SCK. The data are shifted in this register on each falling edge of the serial clock SCK, the data bits are written on the output MISO with the most significant bit first. During all operations, VDD is held stable within the specified operating range.
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Functional description
SCLT3-8BT8
2.5
2.5.1
SPI bus signal description
Chip select /CS
When the chip select signal /CS is high, the data transfer is disabled (SCK and MOSI signals are ignored) and the data output MISO is in high impedance tri-state Z. Driving this input low enables the communication process. At each falling edge of the /CS, the 8 input logic states, and the 8 control bits are loaded into the SPI shift register. The chip select /CS must toggle only when the serial clock signal SCK is in low state.
2.5.2
Serial clock SCK
This clock signal defines the speed and sequence of the SPI communication and is controlled by the master unit. Its transient edges define the serial protocol operation:

The falling edge generates the shift of the data in the register and the last bit writing on the output MISO. The rising edge generates the capture of the data on the input MOSI.
The SCLT internal circuitry secures the SPI operation in mode CPOL = 0, CPHA = 0. When the chip select /CS falls low, the first edge of the clock SCK to be active is always the rising edge. Figure 8. Functional diagram of the SPI logic inputs SCK, MOSI, /CS
VDD
250k 2pF
SCK
2k
ESD HBM
SCLT3-8
2.5.3
Serial data input MOSI
This input signal MOSI is used to shift external data bits into the SCLT register from the most significant (MSB) bit to the least significant one (LSB). The data bits are captured by the SCLT on the rising edge of the serial clock signal SCK. Like the clock SCK, and the chip select /CS, the MOSI input circuit is filtered as shown in Figure 8, in order to match maximum speed operation and improve the EFT burst immunity of the SPI circuit.
2.5.4
Serial data output MISO
This output signal is used to transfer data out of the SCLT slave circuit from the most significant bit (MSB) to the least significant bit (LSB). The first data bit is written out when the chip select /CS goes low. Then the other data bits are written out on the falling edge of the clock signal SCK. The output MISO goes to high impedance tri-state shown on Table 5 when the /CS signal goes in high state.
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SCLT3-8BT8
Functional description
2.5.5
SPI shift register operation selector SPM
The input SPM allows the operation of the SPI shift register to be configured for an 8-bit or 16-bit operation. When SPM is set low (COMP) the shift register runs in a 16-bit mode and transfers both the input state bits and the control bits. When SPM is set high (VDD) the shift register runs in an 8-bit mode and transfers the eight input state bits in a faster transfer process. This SPM input can be changed, and the SPI operation modified, only when the chip select /CS is high (no communication).
2.6
2.6.1
SPI data transfer operation
SPI data frame
The selected structure of the SPI is a 16-bit word in order to be able to implement the input state data and some control bits, such as the UVA alarm, the 4 parity bits and the two low and high state stop bits.
2.6.2
SPI data transfer
The SCLT transfers its 16 data bits through the SPI within one chip select Hi-Lo-Hi sequence. So, this length defines the minimum length that the shift register of the SPI master controller is able to capture 16 bits. Table 3 shows the 16-bit mode in which the data are transferred starting from the data bits, the control bits and ending with a stop bit. Table 3.
Bit # Control
SPI data transfer organization versus SCLT input states with SPM = 0
LSB High Last out Bit 1 Low Bit 2 PC4 Bit 3 PC3 Bit 4 PC2 Bit 5 PC1 Bit 6 /OTA Bit 7 /UVA
Bit # Data
Bit 8 IN 1
Bit 9 IN 2
Bit 10 IN 3
Bit 11 IN 4
Bit 12 IN 5
Bit 13 IN 6
Bit 14 IN 7
MSB IN 8 First out
Table 4.
Bit # Data
SPI data transfer organization versus CLT input states with SPM = 1
Bit 8 IN 1 Last out Bit 9 IN 2 Bit 10 IN 3 Bit 11 IN 4 Bit 12 IN 5 Bit 13 IN 6 Bit 14 IN 7 MSB IN 8 First out
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Functional description
SCLT3-8BT8
2.6.3
SPI transfer speed
The speed of the SPI is defined by the clock frequency and the data frame transfer time. In the SCLT application the transfer time correspond to the input scanning time programmed by the I/O controller. In a 16-bit mode this scanning time should be less than 500 s for a 64-input module (128 bits to transfer) where it should be about 160 s for a 16-input module (32 bits to transfer). To obtain such scanning with the data frame structure, the clock frequency is set respectively at 256 kHz and 200 kHz. Figure 9.
/CS
TLD TCH TCL TF TR THC TDT
SCLT slave unit operation, input MOSI and output MISO timing diagrams
SCK
1
TS
2
TH
15
16
MOSI
TA
MSBM
TD
14
1
TFO TRO
LSBM
MSBS
MISO
MSBS
14
1
LSBS
MSBM
The clock frequency is limited by the application requirements to secure the immunity of the SPI section against fast transient disturbances and keep the isolator consumption low enough. The SCLT maximum SPI clock frequency is 2 MHz.
The minimum SPI clock period is also defined by the capability of the SCLT to capture data on MOSI and to write out data on MISO as shown in Table 9. - - Capture rule: tCH > tH Write out rule: tD + tS < tCL = tC - tCH
At the start of the transfer sequence the first rising edge of the clock SCK should occur after the data writing on the SPI output MISO corresponding with the propagation time tA, avoiding missing the first data: tLD > tA + tS
In between two transfer sequences the output driver of the SPI circuit should go in high impedance before any new transfer operation so falling edge of the chip select /CS: tDIS < tDT .
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SCLT3-8BT8
Functional description
Figure 10. SPI shift register data transfer sequence versus SCLT input states
U VA OTA PC3 PC2 PC4 PC1 IN1 IN2 IN4 IN5 IN7 IN7 IN8 IN3 IN3 IN6 LO LO HI
/CS="1"
MOSI
MSB 0 LSB B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 MSB
MISO
Z
U VA
PC3
PC2
OTA
PC4
PC1
IN1
IN2
IN4
IN5
IN7 IN7
IN8
IN3 IN3
IN6
LO LO
HI
/CS
MOSI
MSB 0 LSB B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 MSB
MISO
MSB
SCK1 SCK1 SCK2
MSB
MSB
LSB
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
MSB
MSB
B14
MSB
MSB
LSB
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B14
B13
B14
B14
MSB
LSB
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B13
SCK15 SCK16
LSB
B1
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
MSB
LSB
LSB
LSB
LSB
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
MSB
LSB
LSB
SCK16
MSB
LSB
LSB
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
MSB
MSB
/CS
MSB
0
LSB
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
MSB
Z
SCK1
MSB
0
LSB
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
MSB
Z
2.7
2.7.1
Control bit signals of the SPI transferred data frame
Power bus voltage monitoring
The UVA circuit generates the alarm /UVA that is active low when the power bus voltage is lower than the activation threshold VCON, 17 V typical, and it is disabled high when the power bus voltage rises above the threshold VCOFF, 18 V typical as shown in Figure 12. The UVA circuit is robust enough to resist ESD and EFT effects, and a filter is added to avoid drop out effects. The analog level can be adjusted externally with a pull down resistor. The power bus voltage is sensed from a separate sensing pin VCS. The overall accuracy is about 15% and the alarm circuit should be insensitive to drop out of less than 1 ms. The under voltage detection does not lead to the SCLT internal shutdown but generates an alarm /UVA that is transmitted through the SPI on control bit #7.
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Functional description Figure 11. UVA circuit block diagram
VCC RS VCS
VBG 1ms delay filter /UVA
SCLT3-8BT8
RPD
COMP
ESD
SCLT3-8
The power supply diagnostics help to determine if the input state is really low or if some power bus failure is damaging the quality of this state signal.
2.7.2
Over temperature alarm
A temperature sensor, equivalent to a diode drop voltage, is placed on the power section of the SCLT in order to sense its operating junction temperature. This protection allows abnormal temperature cases to be detected. The input reverse polarity generates higher current in the inputs, more than twice that shown in the application section, and a maintenance action allows the overall system and functional reliability to be improved. The alarm signal /OTA is enabled, low state active, when the junction temperature is higher than the activation threshold TON, 150 C typical, and it is disabled when the junction temperature falls below the threshold TOFF, 135 C typical as shown in Figure 12. The over temperature detection does not lead to the SCLT internal shutdown but generates an alarm OTA that is transmitted through the SPI on control bit #6. So, it is up to the I/O controller to launch the appropriate action on the system to reduce the constraint in the I/O module. Figure 12. Logic behavior of the OTA and UVA alarm control bits
TOFF
TON
VCCON
VCCOFF
2.7.3
Parity checksum bits calculation and transfer
The aim of the parity checksum bit is to detect one error in the transferred SPI word. Several parity checksum bits are generated and transmitted through the SPI on the control bit #2 to #5. Transmission errors can occur because of the ESD / surge effects or the indirect effects of EFT burst tests beyond the required levels.
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SCLT3-8BT8
Functional description
It is supposed such disturbances affect one bit at a time during the SPI frame transfer. EFT burst repetition rate is about 200 s (5 kHz) and the SPI 16-bit frame should last less than 160 s. A parity bit on the full byte should be obtained by applying an "exclusive NOR" Boolean operation to the eight logic input states (PC1): it goes high when the parity of the 8 inputs is even. The other parity bits PC2 and PC3 are obtained with an "exclusive NOR" Boolean operation respectively on the MSB half data byte (IN5 to IN8) and the LSB half data byte (IN1 to IN4), and PC4 on the middle half data byte (IN3 to IN6): they go high when the parity of the 4 considered inputs is even. These parity bits allow one error to be detected at a time in the SPI data transfer, and this error can be corrected thanks to a second SPI data scan because the corrupted data bit should be statistically different between the two scan sequences. A method is proposed to correct one corrupted input data bit. If full data byte parity bit PC1 is wrong, the first scanned word is stored, and the SCLT input data are scanned immediately twice. Then the first full byte parity bit is checked with its half byte parity bits to confirm the error. The second scanned SPI word is stored and its full byte parity bit is also checked. By using the parity bits on half data byte (the 4 MSB, the 4 LSB, the 4 medium bits), the corrupted input data bit couple of the two scanned SPI words can be detected and the input data byte can be re-synthesized by isolating and replacing these failing bit couples.
2.7.4
SPI hardware interface
All the logic level output signals deliver 80% of VDD for high state and 20% VDD for low state. This SPI circuit is designed to drive CMOS circuit or isolated opto-transistors. Since the clock frequency is always higher than 100 kHz, high speed opto-transistors are selected requiring higher driving input and output currents. The biasing resistors of their output transistors are kept external to allow the speed and the device sourcing to be set for each application, providing thus more flexibility in the choice of these isolators. In Section 3: Application considerations, several cases are proposed for the major applications.
2.7.5
Loss of VCC power supply
The operation of the SCLT is extended beyond the levels required in the IEC 61131-2 standard to allow the implementation of the under voltage alarm UVA as described in Section 2.7.1. If there is no more power feeding on the VCC input, the SCLT chip goes to sleep mode, and the MISO output is forced in low state during SPI transfer attempt. The last SPI control data bit is a stop bit placed normally in high state. The loss of power supply is detected by checking its state. If low, the output is disabled by the internal power reset POR. This POR signal is active in low state when VC is less than 9 V or the internal power supply VDD is less than 3.25 V.
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Functional description Table 5.
POR 1 1 1 0 0
SCLT3-8BT8 Logic state of the SPI output versus the power loss signal POR and the SPI chip select /CS
/CS 1 0 0 1 0
MISO Z 1 0 Z 0
/MISO Z 0 1 Z 1
SPI status Normal with no communiction Normal with communication Normal with communication Power loss with no communication Power loss with communication attempt
Figure 13. Logic status of the SCLT power supply
Power supply status Loss of power UV Alarm Power good
15V
17V
19V
VCC IEC61131-2 level
VC = V CC - RC x (IC + IDD)
~5V 9V 11V 13V
VC
UVA
/CS = Lo
POR
/CS = Lo
MISO
/CS = Lo ; IN ASIC = MISO (non inverting isolator)
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SCLT3-8BT8 Table 6.
Symbol VCC VC ICC VCS VDD IDD VIN IIN LVO LVI VLD IREF IOSC PDIS TJ
Functional description Absolute ratings
Pin VC VC VC VCS VDD VDD INI INI MISO /MISO SCK /CS MOSI LDI REF OSC All All Parameter name and conditions Bus power supply DC voltage, 500 < RC < 2.2 k SCLT power supply voltage, RC = 0 k Maximum bus power supply current Sensing bus power supply voltage Internal logic power supply voltage Maximum logic power supply current Input steady state voltage, RI = 0 , I = 1 to 8 Input forward and reverse current range, RI = 2.2 k Logic output voltage Logic input voltage Maximum LED output voltage, I = 1 to 8 Maximum sourced reference current Maximum sourced oscillator current Maximum dissipation at TAMB= 85 C Storage junction temperature Value - 0.3 to 35 - 0.3 to 30 15 - 0.3 to 6 -0.3 to 6 12 - 0.3 to 30 -20 to +10 -0.3 to 6 -0.3 to 6 3 300 120 850 - 40 to 150 Unit V V mA V V mA V mA V V V A A mW C
Table 7.
Symbol RTH(j-a)
Thermal resistance
Parameter name and conditions Thermal resistance junction to ambient Copper thickness= 35 m, printed board copper surface S = 1 cm Value 80 Unit C/W
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Functional description Table 8.
Symbol VCC VC VCS VDD IDD VI RREF Rosc FIN MAX FSCK tC tCH DCCH tR , tF LVI VLD TAMB Tj SCK SCK SCK SCK SCK, /CS, MOSI LDI ALL Operating junction temperature range
SCLT3-8BT8 Operating conditions
Pin VC VC VCS VDD VDD INI REF OSC Parameter name and conditions Bus power supply steady state voltage, RC > 500 SCLT power supply voltage range Sensing bus power supply voltage, RS = 1.5 M Internal logic power supply voltage Maximum logic power supply current, RC = 500 Input repetitive steady state voltage, RI > 1.8 k Current limiter reference resistance range Filter oscillator resistance range Maximum single input frequency SPI clock frequency range Clock period range Minimum clock active width Clock duty cycle Minimum logic inputs rise and fall times Logic input voltage Maximum LED output voltage, I = 1 to 8 Operating ambient temperature range
(1)
Value 15 to 35 9 to 30 0 to 5 5 10 - 30 to 35 4.7 to 18 15 k to 1.5 M 20 0.1 to 2 0.5 to 10 0.25 50 50 0 to 5.5 2.7 - 25 to 85 - 25 to 150
Unit V V V V mA V k kHz MHz s ns % ns V V C C
1. VI = VIN + RI x IIN , I = 1 to 8
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SCLT3-8BT8 Table 9.
Symbol
Functional description
DC electrical characteristics(1)
Pin Name Conditions Input current limitation Min. Typ. Max. Unit
ILIM VLOW VLIM TH
IN IN IN
Input limiting current Low current input voltage Current limiter activation voltage
VIN = 5.5 to 26 V VCC = 19 V to 30 V TAMB = -25 to + 85 C IIN = 100 A, RI = 0 IIN = 95 % x ILIM_TYP(2)
2.1 -
2.35 2.6 8.5
2.6 3 -
mA V V
Input and supply protection VCL IN, VC Clamping voltage IIN= 7 mA, tP=1 ms, RREF open Input state operation VON VTH_ON VTH_OFF VOFF ION IN IN IN IN LDI On state input voltage Input on state threshold Input off state threshold TAMB = -25 to + 85 C(3) Iin = Ioff = 1.5 A RI = 2.2 k, OFF to ON RI = 2.2 k, ON to OFF C(4) 5 4.5 3.5 2.9 2.0 4.75 3.75 3 2.25 5 4 3.4 2.6 V V V V mA 32.0 38.8 46.0 V
Maximum Off state voltage TAMB = -25 to + 85 On state LED current VI = 11 V Input digital filter
tOSC ROSC tCKF tFT
OSC OSC IN
Oscillator period Oscillator resistance CKF period Filtering time
ROSC = 51 k ROSC = 1200 k
1.17 22 51
1.25 25
1.33 27 1200
s s k
DVR = VDD DVR = COMS 2xtCKF Power supply circuit
64 x tOSC 8 x tOSC 3xtCKF
VRSON VRSOFF IC
VC VC VC
Power on supply voltage Power off supply voltage Supply current
TAMB = - 25 to + 85 C TAMB = - 25 to + 85 C VCC = 30 V, VDD , MISO, /MISO open IDD= 10 mA, CDD = 33 nF, RC = 500 , TAMB = - 25 to + 85 C IDD= 4 mA, CDD = 33 nF TAMB = - 25 to + 85 C Over temperature alarm
8 7.5 1.2
8.5 8.1 1.6
9 8.5 2.3
V V mA
Internal supply voltage VDD VDD Internal supply voltage
4.5
5
5.5
V
4.75
5
5.25
V
TON TOFF
IN IN
Thermal alarm activation Thermal alarm release
-
148 135
-
C C
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Functional description Table 9.
Symbol
SCLT3-8BT8
DC electrical characteristics(1) (continued)
Pin Name Conditions Under voltage alarm Min. Typ. Max. Unit
VCON VOFF ON
VCC VCC VCS VCS VCS
Power voltage alarm Voltage release hysteresis Input activation voltage Input hysteresis voltage Drop out filtering time
RS =1.5 M, RPD =120 k
16 1.25 1
17 1 1.27 0.1 1.7
18 V 1.30 ms
VBG VHY tD_ON
1. TJ = 25 C, VCC = 24 V, RREF = 15 k, RI = 2.2 k, RC = 2.2 k with reference to COMP = COMs voltage, unless otherwise specified. 2. VLIM = VIN + 95 % xILIM x RI 3. Corresponding to VI = 11 V with RI = 2.2 k. 4. Corresponding to VI = 5 V or IIN = 1.5 mA.
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SCLT3-8BT8 Table 10.
Symbol tLD tHC tDT CIN tRC IIN tS tH LVIH LVIL LVOH LVOL tD tRO, tFO tA
1.
Functional description
SPI serial bus link electrical characteristics(1)
Pin SCK SCK /CS SCK, /CS, MOSI MOSI MOSI MOSI SCK, /CS /MISO MISO /MISO MISO /MISO MISO MISO Name Enable lead time Clock hold time Transfer delay time Input capacitance Input filter time constant Input pull up current Data setup time Data hold time Logic input high voltage Logic input low voltage Logic output high voltage Logic output low voltage Write out propagation time Referred to VDD LVI = 0 V MOSI toggling to SCK rising SCK rising to MOSI toggling Share of VDD Share of VDD IOH = 3 mA IOH = 3 mA SCK falling to MISO toggling , CO = 15 pF IMISO = 3 mA CO = 15 pF Output access time /CS falling to MISO toggling Conditions /CS falling to SCK rising SCK falling to /CS rising /CS rising to /CS falling Min. 15 30 4 Typ. 500 10 4 22 4.5 0.45 35 20 20 55 Max. 50 250 30 25 25 70 1 50 50 50 80 Unit ns ns ns pF ns A ns ns % % V V ns ns ns ns
MISO signal fall/rise time
TJ = 25 C, VCC = 24 V, VDD = 5 V with respect to COMS ground pin, unless otherwise specified.
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Functional description Table 11.
Symbol
SCLT3-8BT8 Electromagnetic compatibility ratings(1)
Node
Parameter name and conditions Burst Peak Pulse Voltage: IEC 61000-4-4 class 3 CC = 33 nF, CI = 22 nF, F= 5 kHz, test criteria A ((2) and (3)) Burst Peak Pulse Voltage: IEC 61000-4-4 class 4 CC = 33 nF, CI = 22 nF, F= 5 kHz, test criteria A(2)
Value
Unit
2.5 kV 4 1 2.5 kV 1 15 kV 8 15 kV 8 kV
VPPB
VI
VPP
VI
Surge Peak Pulse Voltage: IEC 61000-4-5 class 3 R = 42 , test criteria B(2) Surge Peak Pulse Voltage: IEC 61000-4-5 class 3, R = 2 , RC = 2.2 k(2) Surge Peak Pulse Voltage: IEC 61000-4-5 class 3, R = 2 , RC = 500 (2) ESD protection, IEC 61000-4-2 class 4, in air Per input to ground, test criteria B
VPP
VCC
VESD
IN ESD protection, IEC 61000-4-2 class 4, in contact Per input to ground COMP, test criteria B ESD protection, IEC 61000-4-2 class 4, in air Test criteria B, CC = 33 nF, RC = 500 ESD protection, IEC 61000-4-2 class 4, in contact Test criteria B, CC = 33 nF, RC = 500
VESD
VCC
1. TJ = 25 C, RI = 2.2 k unless otherwise specified. 2. Respect to ground COMP. Test according to standard with schematic described in application section. 3. Fully functional without any SPI data correction.
Figure 14. Typical limiting current ILIM versus reference resistance RREF
ILIM (mA)
6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0 2 4 6 8 10 12 14 16 18 20
VCC = 24 V VI = 24 V TJ = 25 C
RREF (k)
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SCLT3-8BT8
Functional description
Figure 15. Typical limiting current ILIM versus junction temperature TJ
ILIM (mA) 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2 -25 0 25 50 75 100 125 150 TJ (C)
Rref = 15 k with RIN = 2.2 k, VI = 11 to 30 V, VCC = 11 to 30 V
Figure 16. Relative variation of minimum filter time TFT MIN versus junction temperature TJ
TFT MIN / T FT MIN (25C) 1.15 1.1 1.05 1 0.95 0.9 TJ (C) 0.85 25 50 75 100 125 150
ROSC = 1.2M
ROSC < 150k
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Application considerations
SCLT3-8BT8
3
3.1
Application considerations
SCLT serial link configurations
As long as /CS is low, a slave is able to transmit data bits whatever the length of the data frames. This feature allows several SCLT circuits to be connected in a daisy chain configuration. In the daisy chain configuration with several SCLT circuits (N) all the circuits are addressed by the same chip select and receive the clock signals from the same clock. They all work synchronously. The SPI output MISO of the previous SCLTP-1 device is connected to the SPI input MOSI of the next SCLTP device and the output MISO of the last SCLTN is connected to the MISO input of the master. The MOSI of the first SCLT1 can be kept open or grounded. So, the SPI master reads the whole chain of N 16-bit words starting with the word of the last SCLTN and ending with the word of the first SCLT1. Detailed considerations on SPI operation and daisy chain configurations are also described in ST application notes AN2846 and AN2853. Figure 17. SCLT connection to opto-couplers, bus controller SPI master, and output driver
Case 1: 16-DI
SCK SCK
Case 2: 8-DI and 8-DO
SCLT 2
SCK SCK
SCLT
MISO
MISO MOSI
MISO
MISO
/CS1 /CS2
/CS
/CS
/CS SCK
SCK SDI SDO
VNI8200XP
SCLT 1
MOSI
MOSI MISO
SPI master
MOSI /CS
SPI master
/CS
= 1Mbps coupler
The configuration of the SCLT slave bus circuit allows the master bus controller to operate with other slave circuits in a different phase and polarity mode as long as it runs communication with SCLT in CPHA = 0 and CPOL = 0. The requirement to transfer data in a daisy chain configuration is to use an SPI control master circuit that is able to send and receive a bit stream from 8 minimum up to 128 within one chip select sequence depending on the number of SCLTs and SPI mode (8- or 16-bit).
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Application considerations
3.1.1
Interfacing the SPI section to the I/O controller through optotransistors
Figure 18. Opto-couplers connection between dual SCLT circuit and their master bus controller
VDD1 5V.REG
100nF
SCK
330W
VDD1 CCK SCK RCK
To LED
/CS
330W
ACPL-K73L
SCLT3 - 8
MISO
330W
330W
SPI master Controller VDD2
VDD2
100nF
RMI COMS
330W
MISO
VOUT
ACPL-W70L
CMI
SPI data output
LED ON OFF VOUT HIGH LOW
FCK < 1MHz
RCK, RCS , RMI 220 220
CCK, CCS, CMI 470pF
3.2
High speed operation with magnetic isolators
Figure 19. Connection of SCLT with a magnetic or capacitive coupler for alarm active in low level
VDD1
MISO
Alarm = low
SPI VDD1
/MISO
VDD1
VDD2
VDD2
MISO
VDD2
SCLT
Isolator
SPI master
Magnetic isolators are suitable for higher frequency operation, above 1 MHz, because of their lower current consumption. But their primary power supply loss leads to a high state output that is not compatible with an alarm strategy active in low state as with SCLT. To overcome this issue, two inverting logic buffers can be implemented in the SPI hardware chain. The ASIC will also detect a primary supply loss with a low state. The SCLT is designed providing both MISO and /MISO in order to simplify this hardware environment as shown on Figure 19.
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Application considerations
SCLT3-8BT8
3.3
Reverse polarity robustness
Any reverse polarity of an input INI generates some negative current in the circuit that does not disturb the operation of the other input channels as long as the power supply is working properly (VCC >19 V). Such a case is not dissipative for the SCLT, < 15 mW per input, but consideration should be given to the input resistors. A resistance of RIN = 2.2 k should produce a dissipation of 0.38 W at VI = 30 V. The dissipation rating of the input resistor is set according to the duration of this situation. The power supply VC withstands also this kind of stress, the whole circuit being disabled.
3.4
Surge voltage immunity
Figure 20. Surge voltage test diagram of the SCLT circuit
VPPS = +/- 1kV with 2 VCC RC VC VPPI I VPPS VPP RI IN1 RI RI IN2
VPPI = +/- 1kV with 42 VPPI GND
SCLT3-8
COMP 5 nF PE/FE
The input and supply pins are designed to withstand electromagnetic interferences. They are protected by a clamping function that is connected to the ground pin COMP . Combined with the serial input resistance RI, this clamping protection is effective against the fast transient bursts ( 4 kV, IEC 61000-4-4) and the voltage surges ( 1 kV, IEC 61000-4-5). This topology allows the surge voltage to be applied from each input to other inputs, the ground and the supply contacts in differential or common modes as shown on Figure 20. Thanks to its high resistance RC = 500 , the supply pin VC withstands 1 kV surge voltage according to IEC 61000-4-5 using same diagram as Figure 20. With RC = 2.2 k, this power supply pin withstands more than 2.5 kV.
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Application considerations
3.5
3.5.1
Fast transient burst immunity
Considerations on the power section
The EFT protection is achieved with the same strategy as ESD and surge protection. An input capacitor CI can be added to meet mainly the IEC 61000-4-6 conducted RFI immunity. These capacitors play a key role in suppressing front-end electrical stresses. Their capacitance can be about 22 nF (to validate by test for both EFT and RFI tests). Detailed considerations for EMC performances, board design precautions and component selections are also described in ST application notes AN2846 and AN2853.
3.5.2
Considerations on the logic section
The SPI section is not submitted directly to the transient burst disturbance because this disturbance is applied to the logic input wires and the power supply wires. Since the power section is protected with the clamping diodes, their serial impedance and the digital filters, the logic section and the serial interface is protected against the effects of transients. Nevertheless, the SPI section may be submitted to indirect effects of the EFT transients. So, the design of the power supplies (VCC and VDD), the opto-transistors, and the printed circuit board are done with care to minimize the layout influences. As shown on the suggested opto-transistor schematic on Figure 13, some RC network and power supply decoupling capacitors should be added to meet the reinforced immunity level up ot 2 MHz operation.
3.6
Under voltage alarm setting for IEC and device-net applications
The power supply voltage VCC is monitored by the UVA block through the input resistance RS and RPD: - - - VCON = VBG x (1 + RS/RPD) VCOFF = (VBG + VHY) x (1 + RS/RPD) With VBG = 1.26 V and VHY = 0.1 V
For IEC 6131 PLC applications, the alarm /UVA is activated when the power bus voltage is lower than the activation threshold VCON, 17 V typical, and is released when the power bus voltage rises above the threshold VCOFF, 18 V typical. In this application, the resistances are set to RS = 1.5 M and RPD = 120 k. For device-net applications, the sensor power supply voltage can vary from 11 V to 25 V. The UVA alarm is set between the lower value and the SCLT minimum operation that is set at 9 V. The power supply resistor RC is reduced to match the minimum voltage VCC with the device current consumption. The VC pin robustness could be increased with an additional clamping diode DZ to fit the 1 kV surge requirement. In this case an RC resistance of 150 and an SMAJ30A TransilTM diode are indicated.
TM Transil is a trademark of STMicroelectronics
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Application considerations
SCLT3-8BT8
Figure 21. Power supply connection versus IEC 61131-2 norm levels (left) and device-net norm levels (right)
VCC
RC
VC
SCLT3 -8
5V.REG
DZ = SMAJ30A
VCC
RC DZ
VC
SCLT3 -8
5V.REG
RS RPD
VCS UVA
RS RPD
VCS UVA
3.7
Input operation for the device-net applications
If the sensor connected to the SCLT input has a drop voltage less than 1 V, this input runs with an on-state threshold equal to 10 V. Reducing the input resistance RIN = 1.8 k, the SCLT input meets such an operation.
3.8
Dissipation calculation in the SCLT3-8 circuit
Table 12.
Circuit V Regulator Current limiter Quiescent current
Evaluation of dissipation in the SCLT3-8(1) with RC = 500 and IDD = 7 mA
Count 1 8 1 Drop voltage (V) 30 - 500 x 0.007 - 5 = 21.5 30 - 2200 x 0.0026 = 24.3 30 - 500 x 0.0018 = 29.1 Current (mA) 7 < 2.6 1.8 Total Losses (mW) 150 505 53 708
1. Its thermal resistance is less than : 90 C/W corresponding to T = 150 - 85 = 65 C, PD = 708 mW.
Figure 22. Relative variation of junction-to-ambient thermal resistance RTH_JA versus printed circuit board copper surface SCU
Rth(j-a) (C/W)
120 100 80 60 40 20 SCU (mm) 0 0 20 40 60 80 100 120 140 160 180
Printed circuit board, FR4 epoxy single layer, copper thickness = 35 m
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SCLT3-8BT8
Ordering information scheme
4
Ordering information scheme
Figure 23. Ordering information scheme
SCLT 38 B T8
SCLT = Serial output current limiting termination
3 = 3 mA current setting
8 = Eight channels
B = EMC Level 1 kV according to IEC 61000-4-5 T8 = HTSSOP-38 package
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Package information
SCLT3-8BT8
5
Package information

Epoxy meets UL94, V0 Lead-free packages
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. The SCLT3-8 is packaged in the HTSSOP-38 exposed pad that improves the ground cooling transfer of the input dissipation to the printed board. Increasing the copper surface helps to reduce any hot point on the board. Table 13. HTSSOP-38 dimensions
Dimensions
38 20
Ref.
Millimeters Min. Typ. 0.9 9.70 4.40 0.50 6.40 0.60 6.50 3.20 Max. 1.1 0.15 0.95 0.27 0.20 9.80 4.50 0.70 6.60 3.30 8 Min. 0.002 0.007 0.003
Inches Typ. Max. 0.043 0.006 0.011 0.008
E E1
A A1 A2
c
0.05 0.85 0.17 0.09 9.60 4.30 0.50 6.40 3.10 0
0.033 0.035 0.037
1 D b
e 19 A2 A P A1
b c D E1 e E L P P1 O
14 0.25 mm
0.378 0.382 0.386 0.169 0.173 0.177 0.020 0.252 -
L
O
P1
0.020 0.024 0.027 0.252 0.256 0.260 0.122 0.126 0.130 0 8
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SCLT3-8BT8 Figure 24. SCLT3-8BT8 footprint (dimensions in mm)
0.5
Package information
1.30 0.60
7.10
4.50
3.30
0.3
6.60
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Ordering information
SCLT3-8BT8
6
Ordering information
Table 14. Ordering information
Marking SCLT3-8BT8 SCLT3-8BT8 Package HTSSOP-38 HTSSOP-38 Weight 114 mg 114 mg Base qty 2500 50 Delivery mode Tape and reel Tube
Order code SCLT3-8BT8-TR SCLT3-8BT8
7
Revision history
Table 15.
Date 17-Nov-2008 04-May-2009 02-Nov-2009
Document revision history
Revision 1 2 3 Initial release. Updated mechanical data for package HTSSOP-38. Updated parameters in Table 9 and Table 10. Added Figure 14, Figure 15, Figure 16, and Figure 22. Changes
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